Designing efficient input interconnect blocks for LUT clusters using counting and entropy

  • Authors:
  • Wenyi Feng;Sinan Kaptanoglu

  • Affiliations:
  • Actel Corporation, Mountain View, CA;Actel Corporation, Mountain View, CA

  • Venue:
  • Proceedings of the 2007 ACM/SIGDA 15th international symposium on Field programmable gate arrays
  • Year:
  • 2007

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Abstract

In a cluster-based FPGA, the interconnect from external routing tracks and cluster feedbacks to the LUT inputs consumes significant area, and no consensus has emerged among different implementations (e.g., 1-level or 2-level). In this paper, we model this interconnect as a unified input interconnect block (IIB). We develop general combinatorial techniques to count the number of distinct functional configurations of an IIB. We use entropy, defined as the logarithm of this count, to estimate an IIB's routing flexibility. This enables us to analytically evaluate different IIBs without the customary time-consuming place and route experiments. We show that both depopulated 1-level IIBs and VPR-style 2-level IIBs achieve high routing flexibility but lack area efficiency. We propose a novel class of highly efficient, yet still simple, IIBs that use substantially fewer switches (as few as 1/3) with only a small degradation in routing flexibility. Experimental results verify the routability of these IIBs, and confirm that entropy is a good predictor of routability.