Instruction fetch techniques using program equivalence

Authors:
Douglas E. Eastwood
Affiliations:
University of Wyoming, Laramie, Wyoming
Venue:
ACM SIGMICRO Newsletter
Year:
1974

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Abstract

This paper discusses potential techniques for the dynamic generation of instructions in the instruction fetch unit of a processor. The chief advantage is the increased effective bandwidth in transfer of compressed program information from memory to the processor unit, which allows higher processor speed for a given memory access rate. The method is independent of cache memory techniques, although aimed at the same problem, and could be combined with use of a cache memory to obtain still more speedup of processor execution. The paper is largely at a conceptual level; work is planned to obtain data to facilitate design and simulation of a prototype machine.