Completeness and predicate-based abstract interpretation
PEPM '93 Proceedings of the 1993 ACM SIGPLAN symposium on Partial evaluation and semantics-based program manipulation
Hazard-non-increasing gate-level optimization algorithms
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Making abstract interpretations complete
Journal of the ACM (JACM)
A unified approach to global program optimization
POPL '73 Proceedings of the 1st annual ACM SIGACT-SIGPLAN symposium on Principles of programming languages
POPL '77 Proceedings of the 4th ACM SIGACT-SIGPLAN symposium on Principles of programming languages
Systematic design of program analysis frameworks
POPL '79 Proceedings of the 6th ACM SIGACT-SIGPLAN symposium on Principles of programming languages
Delay Models for Verifying Speed-Dependent Asynchronous Circuits
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Completeness in Abstract Interpretation: A Domain Perspective
AMAST '97 Proceedings of the 6th International Conference on Algebraic Methodology and Software Technology
Refining and Compressing Abstract Domains
ICALP '97 Proceedings of the 24th International Colloquium on Automata, Languages and Programming
Domain Compression for Complete Abstractions
VMCAI 2003 Proceedings of the 4th International Conference on Verification, Model Checking, and Abstract Interpretation
Checking Safety Properties of Behavioral VHDL Descriptions by Abstract Interpretation
SAS '02 Proceedings of the 9th International Symposium on Static Analysis
Formal Methods in System Design
Complexity of flow analysis, inductive assertion synthesis and a language due to Dijkstra
SFCS '80 Proceedings of the 21st Annual Symposium on Foundations of Computer Science
Compositional timing analysis: power plant protection system case study
Proceedings of the 1st International Workshop on Worst-Case Traversal Time
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A technique, based upon abstract interpretation, is presented that allows general gate-level combinational asynchronous circuits with uncertain delay characteristics to be reasoned about. Our approach is particularly suited to the simulation and model checking of circuits where the identification of possible glitch states (static and dynamic hazards) is required. We present a concrete model based upon signals represented as (possibly non-deterministic) functions from absolute dense time to the Booleans, and a hierarchy of achronous abstractions linked by Galois connections, each model offering varying tradeoffs between accuracy and complexity. Many of these abstract domains resemble extended, multi-value logics: transitional logics that include extra values representing transitions as well as steady states, and static/clean logics that include the values S and C representing 'unknown but fixed for all time' and 'can never glitch' respectively. Our framework captures several pre-existing analyses as particular instances in the hierarchy of abstractions.