Algebraic laws for nondeterminism and concurrency
Journal of the ACM (JACM)
A protocol test generation procedure
Computer Networks and ISDN Systems
A linear-time model-checking algorithm for the alternation-free modal mu-calculus
Formal Methods in System Design - Special issue on computer-aided verification: special methods II
Communication and Concurrency
Verification in XESAR of the Sliding Window Protocol
Proceedings of the IFIP WG6.1 Seventh International Conference on Protocol Specification, Testing and Verification VII
Performance evaluation and verification of communication protocol for railway signaling systems
Computer Standards & Interfaces
Computer Standards & Interfaces
Performance analysis and verification of safety communication protocol in train control system
Computer Standards & Interfaces
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Verification and testing are complementary techniques that are used to increase the level of confidence in the correct functioning of communication systems as prescribed by their specifications. This paper presents an experience of model checking for Korean railway signaling protocol specified in LTS (Labeled Transition System). This formal approach checks deadlock, livelock and reachability for the state and action to verify whether properties expressed in modal logic are true on specifications. We also propose a formal method for semi-automated test case generation for Korean railway signaling protocol described in I/O FSM (Input/Output Finite State Machine). This enables the generation of more complete and consistent test sequence for conformance testing. The above functions are implemented by C++ language and included within RSPVTE (Railway Signaling Protocol Verification and Testing Environment) in the MS-windows environment.