Quantifying software performance, reliability and security: An architecture-based approach

  • Authors:

  • Vibhu Saujanya Sharma;Kishor S. Trivedi

  • Affiliations:

  • Department of Computer Science and Engineering, Indian Institute of Technology Kanpur, Kanpur, UP 208016, India;Department of Electrical and Computer Engineering, Duke University, Durham, NC 27708, USA

  • Venue:
  • Journal of Systems and Software
  • Year:
  • 2007

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Abstract

With component-based systems becoming popular and handling diverse and critical applications, the need for their thorough evaluation has become very important. In this paper we propose an architecture-based unified hierarchical model for software performance, reliability, security and cache behavior prediction. We employ discrete time Markov chains (DTMCs) to model software systems and provide expressions for predicting the overall behavior of the system based on its architecture as well as the characteristics of individual components. This approach also facilitates the identification of various bottlenecks. We illustrate its use through some case studies and also provide expressions to perform sensitivity analysis.