Low-voltage limitations of deep-sub-100-nm CMOS LSIs: view of memory designers

Authors:
Kiyoo Itoh;Masanao Yamaoka;Takayuki Kawahara
Affiliations:
Hitachi Ltd., Kokubunji, Tokyo, Japan;Hitachi Ltd., Kokubunji, Tokyo, Japan;Hitachi Ltd., Kokubunji, Tokyo, Japan
Venue:
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Year:
2007

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Ultra-Low Voltage Nanoscale Memories (Series on Integrated Circuits and Systems)

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Abstract

Deep-sub-100-nm CMOS LSIs using a bulk CMOS device and a planar double-gate FD-SOI device are compared in terms of the low-voltage limitation of RAM cells, sense amplifiers, and logic gates. The limitation strongly depends on the ever-larger VT variation, especially in SRAM cells and logic gates, and is improved by the FD-SOI. Consequently, two possible LSIs are predicted to coexist in the deep-sub-100-nm generation: High-VDD bulk CMOS LSIs for low-cost low-standby-current applications, and low-VDD FD-SOI LSIs for low-power applications.