Sensitive registers: a technique for reducing the fetch bandwidth in low-power microprocessors

Authors:
A. Robinson;J. D. Garside
Affiliations:
The University of Manchester, Manchester, United Kingdom;The University of Manchester, Manchester, United Kingdom
Venue:
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Year:
2007

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Abstract

Reducing power consumption is an increasingly important consideration in a wide variety of systems. One source of inefficiency in a 'general purpose' computing system is the (often repeated) overhead of fetching instructions which are used to direct the algorithm rather than process the data directly. This paper proposes a mechanism for the association of frequently used control information with the processor's registers, removing the need to fetch it repeatedly from the instruction stream. Some results are presented to demonstrate both power savings and speed gains over an existing low-power system and the potential for further savings in other programming models is explored.