Hardware architecture for matrix factorization in mimo receivers

  • Authors:
  • Barbara Cerato;Guido Masera;Peter Nilsson

  • Affiliations:
  • Politecnico di Torino, Torino, Italy;Politecnico di Torino, Torino, Italy;Lund University, Lund, Sweden

  • Venue:
  • Proceedings of the 17th ACM Great Lakes symposium on VLSI
  • Year:
  • 2007

Quantified Score

Hi-index 0.00

Visualization

Abstract

This paper presents the hardware realization of the factorization algorithm required in a MIMO OFDM receiver to make the detection and decoding a non-orthogonal space-time code. Requirements of a real scenario represented by the standard IEEE 802.11n for WLAN have been analyzed and exploited to draw out the specifications of the proposed implementation. A very high throughput hardware realization has been obtained able to factorize 128 8x8 real channel matrices during the channel updating period of 28 &3956;s, with a final throughput of 4,63 millions of matrices processed per second. Synthesis results on both 0.13 &3956;m CMOS standard cell technology and FPGA compare favourably to previous implementations.