A high-level simulation and synthesis environment for ΔΣ modulators
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A Sigma-Delta ADC design automation tool with embedded performance estimator
Integration, the VLSI Journal
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In this paper, a tool generated in MATLAB environment for automatic modeling and architecture synthesis of sigma-delta (SD) modulators is described. The tool is capable of generating the parametric signal and noise transfer functions (STF and NTF) of an SD modulator of any order. After generating the transfer functions, it optimizes both the STF and the NTF of the system simultaneously in such a way to realize a desired frequency response. Most important of all, this tool is capable of taking component non-idealities into account and optimizing the coefficients so as to compensate the effects of non-idealities on the system. Integrator non-idealities (the switched capacitor mismatches and integrator leakage due to finite DC gain of the op-amp, etc.) are given as examples in the paper. The tool uses some criteria such as minimization of the number of signal paths of the architecture in order to obtain minimum possible complexity and avoiding of single closed loops without a delay. Also, another important aspect of the tool is that it spans the whole solution space according to this criterion and returns a set of several parametric solutions.