Low Power Small Area Modified Booth Multiplier Design for Predetermined Coefficients*This research was supported by the MIC (Ministry of Information and Communication), Korea, under the ITRC (Information Technology Research Center) support program supervised by the IITA (Institute of Information Technology Assessment) (IITA-C1090-0603-0024).

Authors:
Yong-Eun Kim;Kyung-Ju Cho;Jin-Gyun Chung
Affiliations:
The authors are with the Dept. of Electronics & Information Engr. at Chonbuk National University, Jeonju, Korea. E-mail: kjcho@chonbuk.ac.kr;The authors are with the Dept. of Electronics & Information Engr. at Chonbuk National University, Jeonju, Korea. E-mail: kjcho@chonbuk.ac.kr;The authors are with the Dept. of Electronics & Information Engr. at Chonbuk National University, Jeonju, Korea. E-mail: kjcho@chonbuk.ac.kr
Venue:
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Year:
2007

Citing 0
Cited 2

High-level synthesis algorithm for the design of reconfigurable constant multiplier

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Analysis of twiddle factor memory complexity of radix-2ipipelined FFTs

Asilomar'09 Proceedings of the 43rd Asilomar conference on Signals, systems and computers

Quantified Score

Hi-index	0.00

Visualization

Abstract

In this paper, based on the variation of the modified Booth encoding method, an efficient modified Booth multiplier design method for predetermined coefficient groups is proposed. In the case of pulse-shaping filter design used in CDMA, it is shown that by the proposed method, area and power consumption can be reduced up to 44% and 48%, respectively, compared with the conventional designs. Also, it is shown that in the case of 128-point radix-24 FFT, the area and power consumption can be reduced by 18% and 36%, respectively.