A novel VLSI layout fabric for deep sub-micron applications
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Optimization of throughput performance for low-power VLSI interconnects
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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The determination of metal wire dimensions and inter-layer dielectric thicknesses has become increasingly important in recent times, as wire delays have begun to dominate transistor delays. In this paper, we propose metrics to guide the determination of these dimensions, along with results which describe the efficacy of these metrics. The first metric, which we refer to as cross-bar bandwidth(CBB), compares different wiring configurations in terms ofthe resulting bandwidth they can support in a square of unitsize. The second metric, called power-adjusted cross-bar bandwidth (PCBB), measures the bandwidth of a square, while accounting for the power consumed by the interconnect in the square. The application of these metrics suggests that the traditional approach (of fabricating interconnect of the finest pitch possible) may be sub-optimal with respect to either metric that we present. We have conducted our experiments for layers METAL1 through METAL4, although the approach is general and can be applied to the problem of determining interconnect dimensions for any layer. Without considering driver resistance, our approach yields up to 16% improvement in CBB and 19% improvement in PCBB. When drivers are modeled, the improvements are even greater.