Manolis G.H. Katevenis;Robert W. Sherburne, Jr.;David A. Patterson;Carlo H. Séquin
Stanford Univ., Stanford, CA;Rensselaer Polytechnic Institute, Troy, NY;Univ. of California, Berkeley;Univ. of California, Berkeley
Scheduling expressions on a pipelined processor with a maximal delay of one cycle
ACM Transactions on Programming Languages and Systems (TOPLAS)