VLSI implementation of greedy-based distributed routing schemes for ad hoc networks

  • Authors:

  • Alberto Aloisio;Vincenzo Izzo;Salvatore Rampone

  • Affiliations:

  • Università di Napoli “Federico II”, Dipartimento di Scienze Fisiche and INFN, Napoli, Italy;Università di Napoli “Federico II”, Dipartimento di Scienze Fisiche and INFN, Napoli, Italy;Università del Sannio, Research Centre on Software Technology (RCOST) and DSGA, Benevento, Italy

  • Venue:
  • Soft Computing - A Fusion of Foundations, Methodologies and Applications
  • Year:
  • 2007

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Abstract

We describe a VLSI implementation based on a FPGA of a new greedy algorithm for approximating minimum set covering in ad hoc wireless network applications. The implementation makes the algorithm suitable for embedded and real-time architectures. The algorithm, while not randomized, is based on a probability distribution that leads the greedy choice. The algorithm has been specifically tailored to run on platforms with minimal computational hardware.