An architecture of a dataflow single chip processor
ISCA '89 Proceedings of the 16th annual international symposium on Computer architecture
T: a multithreaded massively parallel architecture
ISCA '92 Proceedings of the 19th annual international symposium on Computer architecture
A design study of the EARTH multiprocessor
PACT '95 Proceedings of the IFIP WG10.3 working conference on Parallel architectures and compilation techniques
Analysis of communications and overhead reduction in multithreaded execution
PACT '95 Proceedings of the IFIP WG10.3 working conference on Parallel architectures and compilation techniques
Converting thread-level parallelism to instruction-level parallelism via simultaneous multithreading
ACM Transactions on Computer Systems (TOCS)
A survey of processors with explicit multithreading
ACM Computing Surveys (CSUR)
Exploiting ILP, TLP, and DLP with the polymorphous TRIPS architecture
Proceedings of the 30th annual international symposium on Computer architecture
Design and implementation of the POWER5™ microprocessor
Proceedings of the 41st annual Design Automation Conference
Proceedings of the 4th international conference on Computing frontiers
Proceedings of the 4th international conference on Computing frontiers
A continuation-based noninterruptible multithreading processor architecture
The Journal of Supercomputing
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Current trends of research on multithreading processors are the chip multithreading (CMT), which aims to exploit thread level parallelism (TLP) and to improve performance of software built onalltraditional threading components, e.g. pthreads. However, CMT is principally a straight forward extension of conventionalall symmetric multiprocessor (SMP) techniques, and it will suffer from the same limits to scalable multithreaded processing ifallit is built only on the traditional sequential-computation-based framework. Consideringallthese limitations of sequential-processor-basedallmultithreading, we are taking another approach to developing a multithreading processor dedicated to thread level parallelism(TLP). Our processor, named Fuce, is based on continuation-based multithreading. A thread is defined as a block of sequentially ordered instructions which areall executed exclusively. Every execution of a thread is triggered by one or more events, each of which is called continuation. The hardware cost and performance of the Fuce processor areallevaluated by means of a hardware implementation on FPGA and software simulation.