VirtualClock: a new traffic control algorithm for packet-switched networks
ACM Transactions on Computer Systems (TOCS)
IEEE/ACM Transactions on Networking (TON)
IEEE/ACM Transactions on Networking (TON)
Efficient fair queueing using deficit round-robin
IEEE/ACM Transactions on Networking (TON)
Latency-rate servers: a general model for analysis of traffic scheduling algorithms
IEEE/ACM Transactions on Networking (TON)
QoS provisioning in clusters: an investigation of Router and NIC design
ISCA '01 Proceedings of the 28th annual international symposium on Computer architecture
MediaWorm: A QoS Capable Router Architecture for Clusters
IEEE Transactions on Parallel and Distributed Systems
ATLAS: A Single-Chip ATM Switch for NOWs
CANPC '97 Proceedings of the First International Workshop on Communication and Architectural Support for Network-Based Parallel Computing
Current issues in packet switch design
ACM SIGCOMM Computer Communication Review
MMR: A High-Performance Multimedia Router - Architecture and Design Trade-Offs
HPCA '99 Proceedings of the 5th International Symposium on High Performance Computer Architecture
A Delay Model and Speculative Architecture for Pipelined Routers
HPCA '01 Proceedings of the 7th International Symposium on High-Performance Computer Architecture
IEEE Transactions on Parallel and Distributed Systems
Providing Quality of Service over Advanced Switching
ICPADS '06 Proceedings of the 12th International Conference on Parallel and Distributed Systems - Volume 1
Implementing the Advanced Switching Minimum Bandwidth Egress Link Scheduler
NCA '06 Proceedings of the Fifth IEEE International Symposium on Network Computing and Applications
Providing full qos support in clusters using only two VCs at the switches
HiPC'05 Proceedings of the 12th international conference on High Performance Computing
Weighted round-robin cell multiplexing in a general-purpose ATM switch chip
IEEE Journal on Selected Areas in Communications
The Network Processing Forum switch fabric benchmark specifications: an overview
IEEE Network: The Magazine of Global Internetworking
High-throughput differentiated service provision router architecture for wireless network-on-chip
International Journal of High Performance Systems Architecture
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Advanced Switching (AS) is an open-standard fabric-interconnect technology that is built over the same physical and link layers as PCI Express technology. Moreover, it includes an optimized transaction layer to enable essential communication capabilities, including protocol encapsulation, peer-to-peer communications, mechanisms to provide quality of service (QoS), enhanced fail-over, high availability, multicast communications, and congestion and system management. In this paper, we propose a strategy to use the AS resources that provides a good performance and QoS support at a low cost. When the system is considered as a whole rather than each element being taken separately, it is possible to use only two virtual channels (VCs) at the switches to provide a service like that with many more VCs. As a result, we obtain a noticeable reduction of silicon area and arbitration time. Our proposal is fully compatible with the AS specification and permits us to provide an adequate performance both for typical multimedia applications and for best-effort traffic.