Effects of property ordering in an incremental formal modeling methodology

Authors:
Syed Suhaib;Deepak Mathaikutty;Sandeep Shukla
Affiliations:
FERMAT Lab., Virginia Polytech. Inst. & State Univ., Blacksburg, VA, USA;FERMAT Lab., Virginia Polytech. Inst. & State Univ., Blacksburg, VA, USA;FERMAT Lab., Virginia Polytech. Inst. & State Univ., Blacksburg, VA, USA
Venue:
HLDVT '04 Proceedings of the High-Level Design Validation and Test Workshop, 2004. Ninth IEEE International
Year:
2004

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XFM: An incremental methodology for developing formal models

ACM Transactions on Design Automation of Electronic Systems (TODAES)

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Abstract

The following topics are dealt with: formal verification; formal specification; processor-oriented validation; decision diagram; validation pattern generation; behavioral modeling; fault coverage analysis; SAT solving; network architecture validation; ...