Exploiting hypergraph partitioning for efficient Boolean satisfiability

Authors:
V. Duraira;P. Kalla
Affiliations:
Dept. of Electr. & Comput. Eng., Utah Univ., Salt Lake City, UT, USA;Dept. of Electr. & Comput. Eng., Utah Univ., Salt Lake City, UT, USA
Venue:
HLDVT '04 Proceedings of the High-Level Design Validation and Test Workshop, 2004. Ninth IEEE International
Year:
2004

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Abstract

The following topics are dealt with: formal verification; formal specification; processor-oriented validation; decision diagram; validation pattern generation; behavioral modeling; fault coverage analysis; SAT solving; network architecture validation; ...