High level hardware validation using hierarchical message sequence charts

  • Authors:

  • P. K. Murthy;S. R. Rajan;K. Takayama

  • Affiliations:

  • Fujitsu Labs. of America, Sunnyvale, CA, USA;California Univ., Riverside, CA, USA;California Univ., Riverside, CA, USA

  • Venue:
  • HLDVT '04 Proceedings of the High-Level Design Validation and Test Workshop, 2004. Ninth IEEE International
  • Year:
  • 2004

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Abstract

We describe a methodology for designing, testing, and verifying hardware designs from a high level of abstraction, using a visual formalism based on hierarchical message sequence charts. We develop a method for generating behaviors and monitors automatically from this high level description, and using it to validate actual hardware implementations developed by design teams. We apply our methodology to the design of a PCl-Express switch, and show that the methodology is useful in finding many design errors. We develop an enhanced hMSC language that can be much better suited for describing complex standards and protocols like the PCI-express.