High performance and cost effective memory architecture for an HDTV decoder LSI

  • Authors:

  • T. Takizawa;J. Tajime;H. Harasaki

  • Affiliations:

  • C&CMedia Res. Labs., NEC Corp., Kawasaki, Japan;-;-

  • Venue:
  • ICASSP '99 Proceedings of the Acoustics, Speech, and Signal Processing, 1999. on 1999 IEEE International Conference - Volume 04
  • Year:
  • 1999

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Abstract

This paper proposes an efficient memory mapping and a frame memory compression for an HDTV decoder LSI using Direct Rambus/sup TM/ DRAM (DRDRAM). The DRDRAM is employed to achieve the high memory bandwidth required for HDTV decoding at the minimum memory cost. The proposed memory mapping achieves a high memory bandwidth sufficient for HDTV decoding even in the worst case and no costly line buffers are required in the LSI for format conversion. The frame memory compression method reduces the memory cost by half and achieves HDTV decoding with a single 64 Mb DRDRAM chip without loss of memory access efficiency. Simulation results show that SNR degradation is 0.1 to 2 dB in the worst frame and no visible degradation is perceived except for a resolution chart sequence.