Efficient 2D FFT implementation on mediaprocessors
Parallel Computing
An implementation of parallel 1-D FFT using SSE3 instructions on dual-core processors
PARA'06 Proceedings of the 8th international conference on Applied parallel computing: state of the art in scientific computing
An implementation of parallel 3-d FFT using short vector SIMD instructions on clusters of PCs
PARA'04 Proceedings of the 7th international conference on Applied Parallel Computing: state of the Art in Scientific Computing
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A fast radix-4 complex FFT implementation using 4-parallel SIMD instructions is presented. Four radix-4 butterflies are calculated in parallel at all stages by loading consecutive 4 elements into a register. At the last stage, every 4 elements is packed into a register and calculated in parallel. This regular data flow enables higher parallelism and an overhead reduction in data format conversion. The implementation result on the V830R processor, which has a 4-parallel SIMD-type multimedia instruction set, achieves practical performance quite competitive with high-end parallel DSPs. Multiply-accumulate instructions with symmetrical rounding introduced to the V830R processor are effective to maintain FFT accuracy.