A new parallel DSP with short-vector memory architecture

Authors:
J. Fridman;W. C. Anderson
Affiliations:
Analog Devices Inc., Norwood, MA, USA;-
Venue:
ICASSP '99 Proceedings of the Acoustics, Speech, and Signal Processing, 1999. on 1999 IEEE International Conference - Volume 04
Year:
1999

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Abstract

This paper presents a new highly-parallel DSP architecture based on a short-vector memory system developed at Analog Devices, Inc. This DSP incorporates for the first time in an embedded processor a number of techniques found in general purpose computing, such as branch prediction, deep and fully interlocked pipeline, and SIMD instruction execution. By means of its short-vector high-bandwidth memory system it is able to deliver sustained performance that is close to its peak computational rates of 1.5 GFLOPS (32-bit floating-point), or 6 GOPS (16-bit fixed-point).