Efficient Stack Simulation for Shared Memory Set-Associative Multiprocessor Caches

  • Authors:

  • C. Eric Wu;Yarsun Hsu;Yew-Huey Liu

  • Affiliations:

  • IBM T. J. Watson Research Center, NY;IBM T. J. Watson Research Center, NY;IBM T. J. Watson Research Center, NY

  • Venue:
  • ICPP '93 Proceedings of the 1993 International Conference on Parallel Processing - Volume 01
  • Year:
  • 1993

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Abstract

We propose efficient stack simulation algorithms for shared memory multiprocessor (MP) caches. A stack simulation algorithm for write-updated MP caches is first presented. It produces the number of write-updates as well as misses for all cache configurations in a single run. We then devise a new stack simulation algorithm for writeinvalidate MP caches. Our algorithm takes into account cross-invalidation among processors, and generates the number of invalidations as well as misses for all cache configurations in a single run. A cache simulator based on our algorithms for MP caches is developed and the results on sample traces are reported. Our results show that effi cient stack simulation is a powerful technique for multi processor cache analysis.