CIPARSim: cache intersection property assisted rapid single-pass FIFO cache simulation technique
Proceedings of the International Conference on Computer-Aided Design
DIMSim: a rapid two-level cache simulation approach for deadline-based MPSoCs
Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
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Trace-driven simulation is the most widely used method to evaluate caches. This demands large amounts of storage and computer time. Several techniques have been proposed to reduce the simulation time of sequential trace-driven simulation. However, little has been done to exploit parallelism. In this paper, we present some efficient parallel simulation techniques that exploit set-partitioning as the main source of parallelism. We show that a straightforward implementation does not give much speedup as one might expect. We develop more efficient parallel simulation techniques by introducing more knowl edge into the cache simulator. The techniques presented here can be efficiently used on multiprocessor worksta tions.