Hierarchical cache/bus architecture for shared memory multiprocessors
ISCA '87 Proceedings of the 14th annual international symposium on Computer architecture
Paradigm: A Highly Scalable Shared-Memory Multicomputer Architecture
Computer - Special issue on cryptography
Hector: A Hierarchically Structured Shared-Memory Multiprocessor
Computer - Special issue on experimental research in computer architecture
LimitLESS directories: A scalable cache coherence scheme
ASPLOS IV Proceedings of the fourth international conference on Architectural support for programming languages and operating systems
The Stanford Dash Multiprocessor
Computer
Performance Analysis of Mesh Interconnection Networks with Deterministic Routing
IEEE Transactions on Parallel and Distributed Systems
Performance and Configuration of Hierarchical Ring Networks for Multiprocessors
ICPP '97 Proceedings of the international Conference on Parallel Processing
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Upper bounds on message delay and throughput are developed for two networks that have been used in recent multiprocessor systems. Two-dimensional mesh networks with bidirectional links and no end-around connections are compared to bus-type hierarchical networks that use segmented rings for the interconnection paths at each level of the hierarchy. Wormhole routing of short, fixed-length messages is used in the mesh networks, while a complete message can be switched between ring segments in one switch time in the hierarchical networks. It is found that three-level hierarchical systems perform somewhat better than mesh systems with respect to the basic bounds criteria that are developed.