Error Recovery in Parallel Systems of Pipelined Processors with Caches

Authors:
Jeng-Ping Lin;Shih-Chang Wang;Sy-Yen Kuo
Affiliations:
National Taiwan University, Taiwan;National Taiwan University, Taiwan;National Taiwan University, Taiwan
Venue:
ICPP '94 Proceedings of the 1994 International Conference on Parallel Processing - Volume 01
Year:
1994

Citing 3
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Abstract

This paper examines the problem of recovering from processor transient faults in pipelined multiprocessor systems. A pipelined machine allows out of order instruction execution and branch prediction to increase performance, thus a precise computation state may not be available. We propose a modified scheme to implement the precise computation state in a pipelined machine. The goal of this research is to implement checkpointing and rollback for error recovery in a pipelined system based on the technique to achieving precise computation state. Detailed analysis has been performed to demonstrate the effectiveness of this method.