Hardware implementation of a genetic controller and effects of training on evolution
ICES'03 Proceedings of the 5th international conference on Evolvable systems: from biology to hardware
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PRISM, a computer architecture consisting of a general-purpose core processor and a reconfigurable FPGA platform, was designed to bridge the gap between general-purpose and specialized computers. PRISM-I, introduced a new concept wherein a custom architecture, utilizing the FPGAs, is dynamically and automatically created to execute a specific C program more efficiently. Speedup is achieved by executing frequently executed functions of the program on the custom-synthesized hardware while the remainder of the program executes on the core processor. PRISM-I, however, being a proof-of-concept system, suffers from several limitations, principal among them being that the evaluation time of a function is restricted to a single bus-cycle, loops with variable iteration counts are not allowed in the function, and control constructs, i.e. "if-then-else", are not executed efficiently. This paper introduces a significant conceptual advancement, PRISM-II, that synthesizes asynchronous, adaptive architectures for C programs and addresses the above limitations of PRISM-I in a general manner. PRISM-II introduces a novel execution model and a framework for translating a C function into an FPGA-based custom architecture.