Stochastic extended Krylov subspace method for variational analysis of on-chip power grid networks
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
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Since the invention of the transistor nearly six decades ago, new technology nodes have been added approximately every two years. This march of progress has yielded smaller transistors that run about 40% faster with each geometry scaling, fulfilling the promise and industry-defining mantra of "smaller, faster, cheaper!" Now, in the realm of 65- and 45-nanometer design and manufacturing, the industry is confronted by multiple complex and stubborn challenges: silicon technology keeps shrinking, but doesn't advance in speed at the same rate.