Comparative Study on SRAMs for Suppressing Both Oxide-Tunneling Leakage and Subthreshold Leakage in Sub-70-nm Leakage Dominant VLSIs

  • Authors:

  • Duk-Hyung Lee;Dong-Kone Kwak;Kyeong-Sik Min

  • Affiliations:

  • Kookmin University, Seoul 136-702, Korea;Kookmin University, Seoul 136-702, Korea;Kookmin University, Seoul 136-702, Korea

  • Venue:
  • VLSID '07 Proceedings of the 20th International Conference on VLSI Design held jointly with 6th International Conference: Embedded Systems
  • Year:
  • 2007

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Abstract

In this paper, we compare 4 SRAM circuits. They are the conventional "SRAM1', "SRAM2' with power switches on VSS line, "SRAM3' with switches on VDD line, and "SRAM4' with switches on VDD and VSS lines, respectively. Among 4 SRAMs, SRAM2 shows the smallest amount of leakage, because its subthreshold leakage is most suppressed by its BODY and DIBL effects. To reduce the oxide-tunneling leakage more, "SRAM5' with lowering of its precharge voltage is considered in this paper. Compared with SRAM2 without lowering of the precharge voltage, the amounts of leakage of SRAM5 are suppressed by 27.2%, 16.8%, and 6.3%, respectively, at -25°C, 25°C, and 100°C.