Cost-effective triple-mode reconfigurable pipeline FFT/IFFT/2-D DCT processor
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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We propose a novel combined wireless baseband processor architecture targeting the Fast Fourier Transform (FFT) for orthogonal frequency division multiplexing (OFDM), the discrete cosine transform (DCT) for video and audio compression, and the modified Walsh transform (MWT) for demodulation of the complementary code key (CCK) in the wireless standard 802.11b. The architecture is variable-length and is suitable for multi-mode and multi-standard OFDM communication systems such as 802.11a, digital audio broadcasting (DAB), digital video broadcasting-terrestrial (DVB-T), very-high-speed digital subscriber loop (VDSL), asymmetric digital subscriber loop (ADSL), and also for 802.11b. It also does joint photographic expert group (JPEG) and moving picture expert group (MPEG) texture en-/decoding. The combined architecture uses 42.5% fewer multipliers, and 35% fewer logic gates in the nonmultiplier hardware, than three individual cores. It has a signalto- noise-ratio (SNR) of 46.5dB with 8 input bits for a 1,024-size FFT. It saves 28.6% of the dynamic and 37% of the static power.