Compiler-directed leakage reduction in embedded microprocessors
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
A framework for power-gating functional units in embedded microprocessors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proceedings of the International Conference on Computer-Aided Design
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Effective power-gating involves deactivating idle functional units for sustained periods incurring little or no performance degradation. Accurate prediction of long idle periods is essential, which, in turn, depends on the application program characteristics. We propose a compiler-based leakage reduction technique for embedded architectures by exploiting the well-known attributes of embedded applications, namely, small code size and intensive loops. From the control flow graph (CFG) representation of the source program, we construct a forest of loop hierarchy trees (LHTs), which capture the nesting loop properties of the program. As an LHT satisfies the partial ordering on the loop nesting, we exploit this property to identify maximal subgraphs (of functional unit idleness) in the original program. For each subgraph so found, a sleep instruction is introduced at the entry point of the corresponding code segement, thus optimizing the number of sleep instructions. The sleep instruction has one operand, a bit-vector comprised of ON/OFF control bits for all functional units in the data path. Our target architecture is a modified ARMprocessor model comprising of functional units with power-gating ability. We obtained 34% average leakage energy reduction for 12 benchmarks chosen from the MiBench suite.