A CMOS Low Voltage Charge Pump

Authors:
Shantanu A. Bhalerao;Abhishek V. Chaudhary;Rajendra M. Patrikar
Affiliations:
Visvesvaraya National Institute of Technology, Nagpur, India;Visvesvaraya National Institute of Technology, Nagpur, India;Visvesvaraya National Institute of Technology, Nagpur, India
Venue:
VLSID '07 Proceedings of the 20th International Conference on VLSI Design held jointly with 6th International Conference: Embedded Systems
Year:
2007

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Abstract

Charge pump circuits are used for obtaining higher voltages than normal power supply voltage in flash memories, DRAMs and low voltage designs. In this paper, we present a charge pump circuit in standard CMOS technology that is suited for low voltage operation. Our proposed charge pump uses a crossconnected NMOS cell as the basic element and PMOS switches are employed to connect one stage to the next. The simulated output voltages of the proposed 4 stage charge pump for input voltage of 0.9 V, 1.2 V, 1.5 V, 1.8 V and 2.1 V are 3.9 V, 5.1 V, 6.35 V, 7.51 V and 8.4 V respectively. This proposed charge pump is suitable for low power CMOS mixed-mode designs.