VLSI array processors
Digital Signal Processing: A Practical Approach
Digital Signal Processing: A Practical Approach
Microwave Mobile Communications
Microwave Mobile Communications
Efficient VLSI Architectures for Multiuser Channel Estimation in Wireless Base-Station Receivers
Journal of VLSI Signal Processing Systems
A complex-number multiplier using radix-4 digits
ARITH '95 Proceedings of the 12th Symposium on Computer Arithmetic
Rapid Scheduling of Efficient VLSI Architectures for Next-Generation HSDPA
RSP '03 Proceedings of the 14th IEEE International Workshop on Rapid System Prototyping (RSP'03)
A rapid prototyping environment for wireless communication embedded systems
EURASIP Journal on Applied Signal Processing
FPGA implementation of an MUD based on cascade filters for a WCDMA system
EURASIP Journal on Applied Signal Processing
IEEE Transactions on Wireless Communications
A DSP-based DS-CDMA multiuser receiver employing partial parallel interference cancellation
IEEE Journal on Selected Areas in Communications
IEEE Journal on Selected Areas in Communications
Adaptive Duplicated Filters and Interference Canceller for DS-CDMA Systems
Journal of Signal Processing Systems
VLSI Implementation of an Adaptive Multiuser Detector for Multirate WCDMA Systems
Journal of Signal Processing Systems
On MSE Exit Chart Analysis and Real Time DSP Implementation for Iterative (Turbo) Detection
Journal of Signal Processing Systems
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This paper investigates real-time DSP and FPGA implementations of a low complexity technique for asynchronous multiuser delay acquisition and time varying channel tracking for multipath channels in WCDMA and cdma2000 systems. A multiuser-LMS-like structure along with smoothing/prediction filters to improve tracking quality is reviewed. We investigate an efficient implementation based on FFT/IFFT technique, under fixed-point data representation and computation constraint. The measured BER reveals that fixed-point implementation is feasible at possibly no performance degradation. Based on real time execution made on a fixed-point high performance DSP, the maximum number of users is 15 and 17 for the proposed method and correlator, respectively. Due to the inherent parallelism and regular data flow FPGA implementation is suggested wherein a maximum number of users more than 80 can be afforded in Xilinx Virtex驴 II Pro device.