Power Aware Design Methodologies
Power Aware Design Methodologies
Leakage aware dynamic voltage scaling for real-time embedded systems
Proceedings of the 41st annual Design Automation Conference
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Factor graphs and the sum-product algorithm
IEEE Transactions on Information Theory
Design of capacity-approaching irregular low-density parity-check codes
IEEE Transactions on Information Theory
Unequal Error Protection Based on DVFS for JSCD in Low-Power Portable Multimedia Systems
ACM Transactions on Embedded Computing Systems (TECS)
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This paper presents a low-power real-time decoder that provides constant-time processing of each frame using dynamic voltage and frequency scaling. The design uses known capacity-approaching low-density parity-check(LDPC) code to contain data over fading channels. Real-time applications require guaranteed data rates. While conventional fixed-number of decoding-iteration schemes are not energy efficient for mobile devices, the proposed heuristic scheme pre-analyzes each received data frame to estimate the maximum number of necessary iterations for frame convergence. The results are then used to dynamically adjust decoder frequency. Energy use is then reduced appropriately by adjusting power supply voltage to minimum necessary for the given frequency. The resulting design provides a judicious trade-off between power consumption and error level.