A write update cache coherence protocol for MIN-based multiprocessors with accessibility-based split caches

Authors:
M. S. Algudady;C. R. Das;M. J. Thazhuthaveetil
Affiliations:
Department of Electrical and Computer Engineering, The Pennsylvania State University, University Park, PA;Department of Electrical and Computer Engineering, The Pennsylvania State University, University Park, PA;Department of Electrical and Computer Engineering, The Pennsylvania State University, University Park, PA
Venue:
Proceedings of the 1990 ACM/IEEE conference on Supercomputing
Year:
1990

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Abstract

In this paper, we present a cache coherence protocol for MIN-based multiprocessors with two distinct private caches: private-block caches containing information private to a processor, and shared-block caches containing data accessible by all processors. The protocol utilizes a coherence control bus (snooping) for connecting all shared-block cache controllers. Timing problems due to variable transit delays through the MIN are dealt with by introducing Transient states in this protocol. Assuming homogeneity of all nodes, a single node queueing model is developed to analyze the system performance. This model is solved using the MVA technique with protocol state probabilities, and few communication delays as input parameters. System performance measures are verified through simulation.