Cache coherence in systems with parallel communication channels & many processors

Authors:
John C. Willis;Arthur C. Sanderson;Charles R. Hill
Affiliations:
The Robotics Institute, CMU and Philips Loboratories, 345 Scarborough Road, Briarcliff Manor, New York;Electrical, Computer and Systems Engineering, RPI and Philips Loboratories, 345 Scarborough Road, Briarcliff Manor, New York;Philips Laboratories, 345 Scarborough Road, Briarcliff Manor, New York
Venue:
Proceedings of the 1990 ACM/IEEE conference on Supercomputing
Year:
1990

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Abstract

This paper describes and analyzes two algorithms for maintaining cache coherence in multiprocessor systems with parallel communication channels and many processors. A distributed link-list relates all cache frames representing the same main memory block. Messages traverse the list to maintain list integrity, exclusive ownership, and consistent values. Memory access semantics are equivalent to a shared memory system without caches. Reference latency, efficiency of memory use, and hardware complexity are moderate and well bounded. This work contributed to the current Scalable Coherence Interface effort; we briefly contrast the two designs.