Modelling Latency-Insensitive Systems in CSP

  • Authors:

  • Hemangee K. Kapoor

  • Affiliations:

  • Dhirubhai Ambani Institute of Information and Communication Technology, India

  • Venue:
  • ACSD '07 Proceedings of the Seventh International Conference on Application of Concurrency to System Design
  • Year:
  • 2007

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Abstract

We survey research works on asynchronous systems synthesis, including PN synthesis and control synthesis.