Serial Parallel Multiplier Design in Quantum-dot Cellular Automata

Authors:
Heumpil Cho;Earl E. Jr. Swartzlander
Affiliations:
Qualcomm, Inc.;University of Texas at Austin
Venue:
ARITH '07 Proceedings of the 18th IEEE Symposium on Computer Arithmetic
Year:
2007

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Abstract

An emerging nanotechnology, quantum-dot cellular automata (QCA), has the potential for attractive features such as faster speed, smaller size, and lower power consumption than transistor based technology. Quantum-dot cellular automata has a simple cell as the basic element. The cell is used as a building block to construct gates, wires, and memories. Several adder designs have been proposed, but multiplier design in QCA is a rather unexplored research area. This paper utilizes the QCA characteristics to design serial parallel multipliers. Two types of serial parallel multipliers are designed and simulated with several different operand sizes. Those designs are compared in terms of complexity, area, and latency. The serial parallel multipliers have simple and regular structures.