Information Theory and Reliable Communication
Information Theory and Reliable Communication
Fault-tolerant wafer-scale architectures for VLSI
ISCA '82 Proceedings of the 9th annual symposium on Computer Architecture
A reconfigurable and fault-tolerant VLSI multiprocessor array
ISCA '81 Proceedings of the 8th annual symposium on Computer Architecture
A complexity theory for VLSI
Synthesis of an Optimal Family of Matrix Multiplication Algorithms on Linear Arrays
IEEE Transactions on Computers
Modeling the Effect of Redundancy on Yield and Performance of VLSI Systems
IEEE Transactions on Computers
Reconfiguring a hypercube in the presence of faults
STOC '87 Proceedings of the nineteenth annual ACM symposium on Theory of computing
The physical mapping problem for parallel architectures
Journal of the ACM (JACM)
The Cubical Ring Connected Cycles: A Fault Tolerant Parallel Computation Network
IEEE Transactions on Computers
IEEE Transactions on Computers
Fault-Tolerant Array Processors Using Single-Track Switches
IEEE Transactions on Computers
A Gracefully Degradable VLSI System for Linear Programming
IEEE Transactions on Computers
Efficient Algorithms for Reconfiguration in VLSI/WSI Arrays
IEEE Transactions on Computers
A Network Flow Approach to the Reconfiguration of VLSI Arrays
IEEE Transactions on Computers
Fault tolerant planar communication networks
STOC '92 Proceedings of the twenty-fourth annual ACM symposium on Theory of computing
Multi-scale self-simulation: a technique for reconfiguring arrays with faults
STOC '93 Proceedings of the twenty-fifth annual ACM symposium on Theory of computing
Harvest Rate of Reconfigurable Pipelines
IEEE Transactions on Computers
Efficiently supporting fault-tolerance in FPGAs
FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays
On finding non-intersecting paths in grids and its application in reconfiguring VLSI/WSI arrays
SODA '90 Proceedings of the first annual ACM-SIAM symposium on Discrete algorithms
Fault-Tolerant Processor Arrays Using Additional Bypass Linking Allocated by Graph-Node Coloring
IEEE Transactions on Computers
IEEE Transactions on Computers
Reconfigurability and Reliability of Systolic/Wavefront Arrays
IEEE Transactions on Computers
New Architecture and Algorithms for Degradable VLSI/WSI Arrays
COCOON '02 Proceedings of the 8th Annual International Conference on Computing and Combinatorics
An improved approach to fault tolerant rank order filtering on a SIMD mesh processor
DFT '95 Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems
A Run-time Reconfiguration Algorithm for VLSI Arrays
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
An improved reconfiguration algorithm for degradable VLSI/WSI arrays
Journal of Systems Architecture: the EUROMICRO Journal
A survey of fault tolerant methodologies for FPGAs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Mapping Homogeneous Graphs on Linear Arrays
IEEE Transactions on Computers
Integrated Row and Column Rerouting for Reconfiguration of VLSI Arrays with Four-Port Switches
IEEE Transactions on Computers
On the reconfiguration algorithm for fault-tolerant VLSI arrays
ICCS'03 Proceedings of the 2003 international conference on Computational science: PartIII
Efficient reconfigurable techniques for VLSI arrays with 6-port switches
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Loop based design for wafer scale systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Behavioral-level synthesis of heterogeneous BISR reconfigurable ASIC's
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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