Computer architecture: a quantitative approach
Computer architecture: a quantitative approach
Efficient trace-driven simulation methods for cache performance analysis
ACM Transactions on Computer Systems (TOCS)
Architectural timing verification of CMOS RISC processors
IBM Journal of Research and Development - Special issue: IBM CMOS technology
Computer organization and design (2nd ed.): the hardware/software interface
Computer organization and design (2nd ed.): the hardware/software interface
Early Performance Estimation of Super Scalar Machine Models
ICCD '91 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
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This paper presents the author's experience in using architectural simulation tools in the instruction of computer architecture courses. In particular, we develop the notion of incrementally building a programmable, trace--driven "timer" tool, for use as a learning vehicle. We show how the cycle--by--cycle simulation output of such timers can be used to illustrate performance bottlenecks, and how this and other output statistics can be interpreted to convey key design tuning issues. As part of the overall simulation toolkit, we also use available cache simulators, trace generators and other utilities in illustrating key performance determinants and architectural trade--off issues.