In-lecture hardware demonstrations with a logic analyzer to illustrate pipelined execution and cache/memory behavior

Authors:
Naraig Manjikian
Affiliations:
Queen's University, Kingston, Ontario, Canada
Venue:
WCAE '00 Proceedings of the 2000 workshop on Computer architecture education
Year:
2000

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Abstract

This paper describes the use of a logic analyzer for in-lecture demonstrations of pipelining and memory hierarchy on representative hardware. The aim is to enhance understanding of fundamental concepts without excessive technical detail. The hardware used in demonstrations is described along with the examples used and their pedagogical aims. Student feedback on this approach is also presented.