First-order incremental block-based statistical timing analysis
Proceedings of the 41st annual Design Automation Conference
Block-based Static Timing Analysis with Uncertainty
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Statistical Timing Analysis Considering Spatial Correlations using a Single Pert-Like Traversal
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Statistical Timing Analysis for Intra-Die Process Variations with Spatial Correlations
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Proceedings of the 42nd annual Design Automation Conference
Correlation-aware statistical timing analysis with non-gaussian delay distributions
Proceedings of the 42nd annual Design Automation Conference
Correlation-preserved non-gaussian statistical timing analysis with quadratic timing model
Proceedings of the 42nd annual Design Automation Conference
Efficient statistical timing analysis through error budgeting
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Critical path selection for delay fault testing based upon a statistical timing model
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Adjustment-based modeling for statistical static timing analysis with high dimension of variability
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Post-silicon timing characterization by compressed sensing
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Statistical static timing analysis: A survey
Integration, the VLSI Journal
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Adjustment-based modeling for timing analysis under variability
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Timing model extraction for sequential circuits considering process variations
Proceedings of the 2009 International Conference on Computer-Aided Design
On hierarchical statistical static timing analysis
Proceedings of the Conference on Design, Automation and Test in Europe
Interpreting SSTA results with correlation
PATMOS'09 Proceedings of the 19th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Fast statistical timing analysis for circuits with post-silicon tunable clock buffers
Proceedings of the International Conference on Computer-Aided Design
Fast statistical timing analysis of latch-controlled circuits for arbitrary clock periods
Proceedings of the International Conference on Computer-Aided Design
Delay-correlation-aware SSTA based on conditional moments
Microelectronics Journal
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The ability to account for the growing impacts of multiple process variations in modern technologies is becoming an integral part of nanometer VLSI design. Under the context of timing analysis, the need for combating process variations has sparkled a growing body of statistical static timing analysis (SSTA) techniques. While first-order SSTA techniques enjoy good runtime efficiency desired for tackling large industrial designs, more accurate second-order SSTA techniques have been proposed to improve the analysis accuracy, but at the cost of high computational complexity. Although many sources of variations may impact the circuit performance, considering a large number of inter-die and intra-die variations in the traditional SSTA analysis is very challenging. In this paper, we address the analysis complexity brought by high parameter dimensionality in static timing analysis and propose an accurate yet fast second-order SSTA algorithm based upon novel parameter dimension reduction. By developing reduced-rank regression based parameter reduction algorithms within block-based SSTA flow, we demonstrate that accurate second order SSTA analysis can be extended to a much higher parameter dimensionality than what is possible before. Our experimental results have shown that the proposed parameter reduction can achieve up to 10X parameter dimension reduction and lead to significantly improved second-order SSTA analysis under a large set of process variations.