Scheduling with bus access optimization for distributed embedded systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on the 11th international symposium on system-level synthesis and design (ISSS'98)
Formal Modeling and Analysis of Advanced Scheduling Features in an Avionics RTOS
EMSOFT '02 Proceedings of the Second International Conference on Embedded Software
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CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Minimising buffer requirements of synchronous dataflow graphs with model checking
Proceedings of the 42nd annual Design Automation Conference
Optimal scheduling using branch and bound with SPIN 4.0
SPIN'03 Proceedings of the 10th international conference on Model checking software
Clock-driven distributed real-time implementation of endochronous synchronous programs
EMSOFT '09 Proceedings of the seventh ACM international conference on Embedded software
Timing analysis of cyber-physical applications for hybrid communication protocols
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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Time-Triggered Protocol for the bus and static task scheduling for the CPU are widely used in safety-critical distributed embedded systems. Researchers have presented efficient heuristic algorithms to jointly optimize static task and bus access schedules. In this paper, we use the model checker SPIN to provide a flexible and configurable technique for obtaining provably optimal solutions, and evaluate its performance tradeoffs compared to heuristic algorithms.