Impact of lens aberrations on optical lithography
IBM Journal of Research and Development - Special issue: optical lithography I
Bounding Circuit Delay by Testing a Very Small Subset of Paths
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
Yield Optimization by Design Centering and Worst-Case Distance Analysis
ICCD '99 Proceedings of the 1999 IEEE International Conference on Computer Design
Statistical Timing Analysis Considering Spatial Correlations using a Single Pert-Like Traversal
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Statistical Timing Analysis for Intra-Die Process Variations with Spatial Correlations
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Correlation-preserved non-gaussian statistical timing analysis with quadratic timing model
Proceedings of the 42nd annual Design Automation Conference
Statistical delay computation considering spatial correlations
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
A statistical framework for post-silicon tuning through body bias clustering
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
A framework for statistical timing analysis using non-linear delay and slew models
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Accurate temperature estimation using noisy thermal sensors
Proceedings of the 46th Annual Design Automation Conference
A statistical framework for designing on-chip thermal sensing infrastructure in nano-scale systems
Proceedings of the 19th international symposium on Physical design
Diagnosis-assisted supply voltage configuration to increase performance yield of cell-based designs
Proceedings of the 16th Asia and South Pacific Design Automation Conference
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Systematic variations with device parameters and critical dimensions are crucial information in achieving higher yields with semiconductor devices. In this paper, we propose a method to extract systematic variation models of segment delays based on the measured path delays of tested chips. First, we cluster chips according to the similarity of the path delay vectors. Then, for each cluster, a hierarchical variation model is built. The extracted models are closely related to the design and can have many potential applications for yield and quality enhancements.