An improved recursive median filtering scheme for image processing
IEEE Transactions on Image Processing
Differential morphology and image processing
IEEE Transactions on Image Processing
Composing morphological filters
IEEE Transactions on Image Processing
Adaptive fuzzy multilevel median filter
IEEE Transactions on Image Processing
A domain operator for binary morphological processing
IEEE Transactions on Image Processing
Video communications using rapidly reconfigurable hardware
IEEE Transactions on Circuits and Systems for Video Technology
Reconfigurable Morphological Image Processing Accelerator for Video Object Segmentation
Journal of Signal Processing Systems
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This paper presents the considerations on selecting a multiprocessor MISD architecture for fast implementation of the vision image processing. Using the author's earlier experience with real-time systems, implementing of specialized hardware processors based on the programmable FPGA systems has been proposed in the pipeline architecture. In particular, the following processors are presented: median filter and morphological processor. The structure of a universal reconfigurable processor developed has been proposed as well. Experimental results are presented as delays on LCA level implementation for median filter, morphological processor, convolution processor, look-up-table processor, logic processor and histogram processor. These times compare with delays in general purpose processor and DSP processor.