A methodology for rapid prototyping peak-constrained least-squares bit-serial finite impulse response filters in FPGAs

  • Authors:

  • Alex Carreira;Trevor W. Fox;Laurence E. Turner

  • Affiliations:

  • Department of Electrical and Computer Engineering, University of Calgary, Calgary, Alberta, Canada;Department of Electrical and Computer Engineering, University of Calgary, Calgary, Alberta, Canada;Department of Electrical and Computer Engineering, University of Calgary, Calgary, Alberta, Canada

  • Venue:
  • EURASIP Journal on Applied Signal Processing
  • Year:
  • 2003

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Abstract

Area-efficient peak-constrained least-squares (PCLS) bit-serial finite impulse response (FIR) filter implementations can be rapidly prototyped in field programmable gate arrays (FPGA) with the methodology presented in this paper. Faster generation of the FPGA configuration bitstream is possible with a new application-specific mapping and placement method that uses JBits to avoid conventional general-purpose mapping and placement tools. JBits is a set of Java classes that provide an interface into the Xilinx Virtex FPGA configuration bitstream, allowing the user to generate new configuration bitstreams. PCLS coefficient generation allows passband-to-stopband energy ratio (PSR) performance to be traded for a reduction in the filter's hardware cost without altering the minimum stopband attenuation. Fixed-point coefficients that meet the frequency response and hardware cost specifications can be generated with the PCLS method. It is not possible to meet these specifications solely by the quantization of floating-point coefficients generated in other methods.