Translational lemmas for DLOGTIME-uniform circuits, alternating TMs, and PRAMs

  • Authors:
  • Chuzo Iwamoto;Naoki Hatayama;Yoshiaki Nakashiba;Kenichi Morita;Katsunobu Imai

  • Affiliations:
  • Hiroshima University, Graduate School of Engineering, 739-8527, Hiroshima, Japan;Sharp Corporation, 545-8522, Osaka, Japan;Mitsubishi Electric Corporation, 100-8310, Tokyo, Japan;Hiroshima University, Graduate School of Engineering, 739-8527, Hiroshima, Japan;Hiroshima University, Graduate School of Engineering, 739-8527, Hiroshima, Japan

  • Venue:
  • Acta Informatica
  • Year:
  • 2007

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Abstract

We present translational lemmas for the three standard models of parallel computation, and apply them to obtain tight hierarchy results. It is shown that, for arbitrarily small rational constant $$\epsilon 0$$, (i) there is a language which can be accepted by a $$U_{\rm E}$$-uniform circuit family of depth $$c(1+\epsilon)(\log n)^{r_1}$$ and size $$dn^{r_2(1+\epsilon)}$$ but not by any $$U_{\rm E}$$-uniform circuit family of depth $$c(\log n)^{r_1}$$ and size $$dn^{r_2}$$, (ii) there is a language which can be accepted by a $$c(9+\epsilon)(\log n)^{r_1}$$-time $$d(4+\epsilon)\log n$$-space ATM with l worktapes but not by any $$c(\log n)^{r_1}$$-time $$d\log n$$-space ATM with the same l worktapes if the number of tape symbols is fixed, and (iii) there is a language which can be accepted by a $$c(1+\epsilon)(\log n)^{r_1}$$-time PRAM with $$dn^{r_2(1+\epsilon)}$$ processors but not by any $$c(\log n)^{r_1}$$-time PRAM with $$dn^{r_2}$$ processors. Here, c  0, d ≥ 1, r 1  1, and r2 ≥ 1 are arbitrary rational constants, and l ≥ 2 is an arbitrary integer.