Networks of spiking neurons: the third generation of neural network models
Transactions of the Society for Computer Simulation International - Special issue: simulation methodology in transportation systems
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The present paper reports the design of a CMOS circuit capable of codifying the natural logarithm of an analog voltage in the relative phase of a train of pulses. The circuit is aimed to the implementation of a scale-independent pattern recognition system, based on the explanation provided by J. Hopfield for the human brain pattern-recognition computation in terms of stimuli representation through the phase of the action potentials. The circuit is designed targeting the AMS 0.35 μm process, occupying a core area of 0.0049 mm2 and with a power consumption of less than 14 μW at a clock frequency of 3.3 MHz. The circuit codifies analog input voltages ranging form 1 to 5 V in phase differences between 2 and 2.7 μs.