Face Recognition by Elastic Bunch Graph Matching
IEEE Transactions on Pattern Analysis and Machine Intelligence
A QCIF Resolution Binary I/O CNN-UM Chip
Journal of VLSI Signal Processing Systems - Special issue on spatiotemporal signal processing with analog CNN visual microprocessors
IEEE Transactions on Pattern Analysis and Machine Intelligence
A Tutorial on Support Vector Machines for Pattern Recognition
Data Mining and Knowledge Discovery
Multiresolution Gray-Scale and Rotation Invariant Texture Classification with Local Binary Patterns
IEEE Transactions on Pattern Analysis and Machine Intelligence
Robust Texture Classification by Subsets of Local Binary Patterns
ICPR '00 Proceedings of the International Conference on Pattern Recognition - Volume 3
Two-Dimensional PCA: A New Approach to Appearance-Based Face Representation and Recognition
IEEE Transactions on Pattern Analysis and Machine Intelligence
A Texture-Based Method for Modeling the Background and Detecting Moving Objects
IEEE Transactions on Pattern Analysis and Machine Intelligence
Visual Characterization of Paper Using Isomap and Local Binary Patterns
IEICE - Transactions on Information and Systems
The CSU face identification evaluation system: its purpose, features, and structure
ICVS'03 Proceedings of the 3rd international conference on Computer vision systems
A discriminative feature space for detecting and recognizing faces
CVPR'04 Proceedings of the 2004 IEEE computer society conference on Computer vision and pattern recognition
Eigenspace-based face recognition: a comparative study of different approaches
IEEE Transactions on Systems, Man, and Cybernetics, Part C: Applications and Reviews
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We present methods for processing the LBPs (local binary patterns) with a massively parallel hardware, especially with CNN-UM (cellular nonlinear network-universal machine). In particular, we present a framework for implementing a massively parallel face recognition system, including a dedicated highly accurate algorithm suitable for various types of platforms (e.g., CNN-UM and digital FPGA). We study in detail a dedicated mixed-mode implementation of the algorithm and estimate its implementation cost in the view of its performance and accuracy restrictions.