Discrete-time signal processing
Discrete-time signal processing
Time-frequency-based detection using discrete-time discrete-frequency Wigner distributions
IEEE Transactions on Signal Processing
Pseudo affine Wigner distributions: definition and kernelformulation
IEEE Transactions on Signal Processing
IEEE Transactions on Signal Processing
Toeplitz and Hankel kernels for estimating time-varying spectra ofdiscrete-time random processes
IEEE Transactions on Signal Processing
Finite word-length effects in implementation of distributions fortime-frequency signal analysis
IEEE Transactions on Signal Processing
Adaptive S-method for SAR/ISAR imaging
EURASIP Journal on Advances in Signal Processing
An efficient hardware design of a system for highly nonstationary signals filtering
ACACOS'08 Proceedings of the 7th WSEAS International Conference on Applied Computer and Applied Computational Science
Journal of Signal Processing Systems
SSIP'05 Proceedings of the 5th WSEAS international conference on Signal, speech and image processing
Hi-index | 0.00 |
Multiple-clock-cycle implementation (MCI) of a flexible system for time-frequency (TF) signal analysis is presented. Some very important and frequently used time-frequency distributions (TFDs) can be realized by using the proposed architecture: (i) the spectrogram (SPEC) and the pseudo-Wigner distribution (WD), as the oldest and the most important tools used in TF signal analysis; (ii) the S-method (SM) with various convolution window widths, as intensively used reduced interference TFD. This architecture is based on the short-time Fourier transformation (STFT) realization in the first clock cycle. It allows the mentioned TFDs to take different numbers of clock cycles and to share functional units within their execution. These abilities represent the major advantages of multicycle design and they help reduce both hardware complexity and cost. The designed hardware is suitable for a wide range of applications, because it allows sharing in simultaneous realizations of the higher-order TFDs. Also, it can be accommodated for the implementation of the SM with signal-dependent convolution window width. In order to verify the results on real devices, proposed architecture has been implemented with a field programmable gate array (FPGA) chips. Also, at the implementation (silicon) level, it has been compared with the single-cycle implementation (SCI) architecture.