Statistical performance modeling and optimization

Authors:
Xin Li;Jiayong Le;Lawrence T. Pileggi
Affiliations:
Department of ECE, Carnegie Mellon University, Pittsburgh, PA;Extreme DA, Palo Alto, CA;Department of ECE, Carnegie Mellon University, Pittsburgh, PA
Venue:
Foundations and Trends in Electronic Design Automation
Year:
2006

Citing 73
Cited 6

Design for manufacturability in submicron domain

Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Efficient analog circuit synthesis with simultaneous yield and robustness optimization

Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
MAELSTROM: efficient simulation-based synthesis for custom analog cells

Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Optimization of inductor circuits via geometric programming

Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Latin hypercube sampling of Gaussian random fields

Technometrics
Design and optimization of LC oscillators

ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
A statistical static timing analysis considering correlations between delays

Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Mismatch analysis and direct yield optimization by specwise linearization and feasibility-guided search

Proceedings of the 38th annual Design Automation Conference
A general probabilistic framework for worst case timing analysis

Proceedings of the 39th annual Design Automation Conference
Simulation and the Monte Carlo Method

Simulation and the Monte Carlo Method
Response Surface Methodology: Process and Product in Optimization Using Designed Experiments

Response Surface Methodology: Process and Product in Optimization Using Designed Experiments
Symbolic Analysis for Automated Design of Analog Integrated Circuits

Symbolic Analysis for Automated Design of Analog Integrated Circuits
Test structures for delay variability

Proceedings of the 8th ACM/IEEE international workshop on Timing issues in the specification and synthesis of digital systems
The sizing rules method for analog integrated circuit design

Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
ASF: a practical simulation-based methodology for the synthesis of custom analog circuits

Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Design of pipeline analog-to-digital converters via geometric programming

Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Exploring regular fabrics to optimize the performance-cost trade-off

Proceedings of the 40th annual Design Automation Conference
Comparison of adaptive body bias (ABB) and adaptive supply voltage (ASV) for improving delay and leakage under the presence of process variation

IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low power
Convex Optimization

Convex Optimization
Automated design of operational transconductance amplifiers using reversed geometric programming

Proceedings of the 41st annual Design Automation Conference
ORACLE: optimization with recourse of analog circuits including layout extraction

Proceedings of the 41st annual Design Automation Conference
Fast statistical timing analysis handling arbitrary delay correlations

Proceedings of the 41st annual Design Automation Conference
Parametric yield estimation considering leakage variability

Proceedings of the 41st annual Design Automation Conference
Statistical timing analysis based on a timing yield model

Proceedings of the 41st annual Design Automation Conference
Impact of Design-Manufacturing Interface on SoC Design Methodologies

IEEE Design & Test
Initial Sizing of Analog Integrated Circuits by Centering Within Topology-Given Implicit Specification

Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Block-based Static Timing Analysis with Uncertainty

Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Statistical Timing Analysis for Intra-Die Process Variations with Spatial Correlations

Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Timing

Timing
Monte Carlo Statistical Methods (Springer Texts in Statistics)

Monte Carlo Statistical Methods (Springer Texts in Statistics)
Parameterized block-based statistical timing analysis with non-gaussian parameters, nonlinear delay functions

Proceedings of the 42nd annual Design Automation Conference
Correlation-aware statistical timing analysis with non-gaussian delay distributions

Proceedings of the 42nd annual Design Automation Conference
Correlation-preserved non-gaussian statistical timing analysis with quadratic timing model

Proceedings of the 42nd annual Design Automation Conference
Design methodology for IC manufacturability based on regular logic-bricks

Proceedings of the 42nd annual Design Automation Conference
Full-chip analysis of leakage power under process variations, including spatial correlations

Proceedings of the 42nd annual Design Automation Conference
Accurate and efficient gate-level parametric yield estimation considering correlated variations in leakage power and performance

Proceedings of the 42nd annual Design Automation Conference
OPERA: optimization with ellipsoidal uncertainty for robust analog IC design

Proceedings of the 42nd annual Design Automation Conference
Statistical static timing analysis: how simple can we get?

Proceedings of the 42nd annual Design Automation Conference
Asymptotic probability extraction for non-normal distributions of circuit performance

Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Robust analog/RF circuit design with projection-based posynomial modeling

Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Robust extraction of spatial correlation

Proceedings of the 2006 international symposium on Physical design
Performance-centering optimization for system-level analog design exploration

ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Projection-based performance modeling for inter/intra-die variations

ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Statistical timing analysis with two-sided constraints

ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Defining statistical sensitivity for timing optimization of logic circuits with large-scale process and environmental variations

ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Criticality computation in parameterized statistical timing

Proceedings of the 43rd annual Design Automation Conference
Mixture importance sampling and its application to the analysis of SRAM designs in the presence of rare failure events

Proceedings of the 43rd annual Design Automation Conference
Projection-based statistical analysis of full-chip leakage power with non-log-normal distributions

Proceedings of the 43rd annual Design Automation Conference
Modeling of intra-die process variations for accurate analysis and optimization of nano-scale circuits

Proceedings of the 43rd annual Design Automation Conference
Design and Analysis of Experiments

Design and Analysis of Experiments
Joint design-time and post-silicon minimization of parametric yield loss using adjustable robust optimization

Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
From Finance to Flip Flops: A Study of Fast Quasi-Monte Carlo Methods from Computational Finance Applied to Statistical Circuit Analysis

ISQED '07 Proceedings of the 8th International Symposium on Quality Electronic Design
Efficient parametric yield extraction for multiple correlated non-normal performance distributions of Analog/RF circuits

Proceedings of the 44th annual Design Automation Conference
Design of Analog CMOS Integrated Circuits

Design of Analog CMOS Integrated Circuits
Transient simulation of integrated circuits in the charge-voltage plane

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Anaconda: simulation-based synthesis of analog circuits via stochastic pattern search

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A new class of convex functions for delay modeling and its application to the transistor sizing problem [CMOS gates]

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Efficient handling of operating range and manufacturing line variations in analog cell synthesis

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Optimal design of a CMOS op-amp via geometric programming

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
CMOS op-amp sizing using a geometric programming formulation

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
AMGIE-A synthesis environment for CMOS analog integrated circuits

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Impact of spatial intrachip gate length variability on the performance of high-speed digital circuits

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A high-level simulation and synthesis environment for ΔΣ modulators

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Statistical timing analysis using bounds and selective enumeration

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Accurate estimation of total leakage in nanometer-scale bulk CMOS circuits based on device geometry and doping profile

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Application-specific worst case corners using response surfaces and statistical models

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Statistical timing analysis under spatial correlations

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
First-Order Incremental Block-Based Statistical Timing Analysis

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Statistical Timing for Parametric Yield Prediction of Digital Integrated Circuits

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Robust Analog/RF Circuit Design With Projection-Based Performance Modeling

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Asymptotic Probability Extraction for Nonnormal Performance Distributions

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Worst-case analysis and optimization of VLSI circuit performances

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Process variation-aware performance analysis of asynchronous circuits

Microelectronics Journal
System-level process variability analysis and mitigation for 3D MPSoCs

Proceedings of the Conference on Design, Automation and Test in Europe
Statistical leakage power optimization of asynchronous circuits considering process variations

PATMOS'10 Proceedings of the 20th international conference on Integrated circuit and system design: power and timing modeling, optimization and simulation
Process variation aware performance analysis of asynchronous circuits considering spatial correlation

PATMOS'09 Proceedings of the 19th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
On confident task-accurate performance estimation

ARCS'13 Proceedings of the 26th international conference on Architecture of Computing Systems
Efficient importance sampling for high-sigma yield analysis with adaptive online surrogate modeling

Proceedings of the Conference on Design, Automation and Test in Europe

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Abstract

As IC technologies scale to finer feature sizes, it becomes increasingly difficult to control the relative process variations. The increasing fluctuations in manufacturing processes have introduced unavoidable and significant uncertainty in circuit performance; hence ensuring manufacturability has been identified as one of the top priorities of today's IC design problems. In this paper, we review various statistical methodologies that have been recently developed to model, analyze, and optimize performance variations at both transistor level and system level. The following topics will be discussed in detail: sources of process variations, variation characterization and modeling, Monte Carlo analysis, response surface modeling, statistical timing and leakage analysis, probability distribution extraction, parametric yield estimation and robust IC optimization. These techniques provide the necessary CAD infrastructure that facilitates the bold move from deterministic, corner-based IC design toward statistical and probabilistic design.